The present invention relates to a semiconductor memory device; and, more particularly, to a semiconductor memory device having improved peripheral circuits with a stable precharge voltage level of data lines.
Generally, since an operation delay is caused in a semiconductor memory device using a low precharge voltage level, a power supply voltage VDD (or peripheral voltage) is used as a precharge voltage to improve a sensing speed of data lines. However, when VDD is used as the precharge voltage, a voltage level of the data lines becomes a ground voltage (VSS) level in a write operation and, thereafter, the voltage level becomes the VDD level at a precharge operation. Therefore, current consumption highly increases in a burst write operation. Specially, the current consumption highly increases in a high density memory device having a high parasitic capacitance of data lines and in a double data rate (DDR) memory device having a plurality of data lines.
A semiconductor memory device comprises peripheral circuits including I/O sense amplifiers, equalizers and write drivers and a core having memory cells. Since a noise is generated by a lot of I/O data from and to a write buffer, different voltage levels are applied to the peripheral circuit and the core in order to avoid the noise.
Also, when a read operation is carried out in a low voltage level, a characteristic of switch performance between data lines are deteriorated, so that a desired data signal cannot be obtained. Accordingly, a stable operation of the I/O sense amplifier cannot be expected.
In order to solve the above problems, a precharge circuit for precharging the data lines with a half core voltage VBLP (Vcore/2) level or a half power supply voltage level (VDD/2) is, recently, used for speedy write and read operations.
FIG. 1 is a schematic block diagram illustrating a typical semiconductor memory device.
The semiconductor memory device includes a plurality of local data line sense amplifiers 110, a plurality of pairs of local data lines 160A and 160B, a plurality of pairs of global data lines 170A and 170B, a switch unit 120, an I/O sense amplifier (IOSA) 130, an equalizing and precharging unit 150 and a write driver 140.
The local data line sense amplifier 110 amplifies data on the local data lines 160A and 160B. The switch unit 120 controls a transfer of the amplified data from the local data lines 160A and 160B to the global data lines 170A and 170B. The I/O sense amplifier IOSA 130, which is connected to the global data lines 170A and 170B, amplifies data read out from a memory cell (not shown) in order to output the data to an external circuit of the semiconductor memory device.
The equalizing and precharging unit 150 equalizes and precharges the global data lines 170A and 170B by supplying half core voltage VBLP to the global data lines 170A and 170B. The write driver 140, which is connected to the global data lines 170A and 170B, is used to write data to the memory cell.
FIG. 2A is a circuit diagram illustrating an exemplary equalizing and precharging unit 150 using only NMOS transistors for precharging the global data lines 170A and 170B according to the prior art.
The equalizing and precharging unit 150 includes a first NMOS transistor NT1 and a second transistor NT2 connected to the global data lines 170A and 170B in series for precharging the global data lines 170A and 170B with a half core voltage VBLP applied between the first NMOS transistor NT1 and the second MOS transistor NT2 and a third NMOS transistor NT3 for equalizing in response to an I/O equalizing signal IOEQ. The I/O equalizing signal is applied to each gate of the NMOS transistors NT1, NT2 and NT3. When the I/O equalizing signal IOEO is enabled with a power supply voltage VDD for the precharge operation, the NMOS transistors NT1 and NT3 are turned on and then, the NMOS transistor NT2 is turned on later than the NMOS transistors NT1 and NT3. Namely, after the burst write operation is completed, when the precharge operation is carried out again, the precharge voltage level of the global data lines 170A and 170B becomes a little bit lower than a previous precharge voltage level because the NMOS transistors NT1 and NT3 are turned on earlier than the NMOS transistor NT2.
Therefore, when the burst write operation is repeatedly carried out, the precharge voltage level of the global data lines 170A and 170B gradually is fallen toward ground voltage vss level.
FIG. 2B is a waveform illustrating a simulation result of the precharge operation of the equalizing and precharging unit 150 of FIG. 2A.
Referring to FIG. 2B, as the burst write operation is repeatedly carried out from WRITE1 to WRITE4, the precharge voltage level is decreased bit by bit toward the ground voltage VSS level.
FIG. 3A is a circuit diagram illustrating another exemplary equalizing and precharging unit 150 using only PMOS transistors for precharging the global data lines 170A and 170B according to the prior art.
The equalizing and precharging unit 150 includes a first PMOS transistor PT1 and a second transistor PT2 for precharging the global data lines 170A and 170B with VBLP and a third PMOS transistor PT3 for an equalizing operation in response to an I/O equalizing bar signal IOEQZ. The I/O equalizing bar signal IOEQZ is applied to each gate of the PMOS transistors PT1, PT2 and PT3. When the I/O equalizing signal bar IOEQZ is enabled with 0 V for the precharge operation, the PMOS transistors PT2 and PT3 are turned on and then, the PMOS transistor PT1 is turned on later than the PMOS transistors PT2 and PT3 Therefore, when the write burst operation is repeatedly carried out, the precharge voltage level of the global data lines 170A and 170B gradually increases toward core voltage Vcore.
FIG. 3B is a waveform illustrating a simulation result of the precharge operation of the equalizing and precharging unit 150 in FIG. 3A.
Referring to FIG. 3B, as the burst write operation is repeatedly carried out from WRITE1 to WRITE4, the precharge voltage level is increased bit by bit toward the core voltage Vcore level.
As mentioned above, when precharging the data lines by using the conventional method, a precharge voltage level is not maintained in a half core voltage VBLP as the burst write operation is repeatedly carried out. Accordingly, there are problems that current consumption is increased and an operation speed becomes slow.
It is, therefore, an object of the present invention to provide a semiconductor memory device reducing current consumption in read/write and precharging operations.
In accordance with an aspect of the present invention, there is provided an equalizing and precharging circuit in a semiconductor memory device, comprising: a pull down equalizing and precharging unit for equalizing and precharging data lines in response to an input/output equalizing signal; and a pull up equalizing and precharging unit for equalizing and precharging data lines in response to an input/output equalizing bar signal.
In accordance with another aspect of the present invention, there is provided a semiconductor memory device, comprising: a local data line sense amplifier for amplifying data, which are on local data lines; a first switching means for controlling data transfer from the local data lines into global data lines; an input/output sense amplifier, which is connected to the global data lines for amplifying and outputting data read out from a memory cell to an external circuit of the semiconductor device; an equalizing and precharging means, which is connected to the global data lines, for equalizing and precharging the global data lines, wherein the equalizing and precharging means includes a first equalizing and precharging unit and a second equalizing and precharging unit for quickly equalizing and precharging the global data lines; and a write driver, which is connected to the global data lines, for writing data to the memory cell.